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Calendar  Date   Topic  Comments   1383/11/18     CAD - topic 1   Introduction   1383/11/20     CAD - topic 1 (cont.)   Introduction   1383/11/25     CAD - topic 2   Design Methodologies - HDLs Introduction   1383/11/27     Verilog - topic 1   Verilog basics - Structural Modeling   1383/12/04     Verilog - topic 2   Continuous Assignment, Operators   1383/12/09     Verilog - topic 3   Procedural Blocks, Blocking & Non-Blocking Assignment   1383/12/11     Verilog - topic 3 (cont.) & CAD - topic 3   Verilog Examples & ASIC Design   1383/12/16     CAD - topic 3 (cont.) & topic 4   ASIC Design and PLDs   1383/12/18     Verilog - topic 4   Behavioral Statements   1383/12/23     CAD - topic 5   FPGAs   1384/01/14     Verilog Example   Dice Game   1384/01/16     Verilog Example   Multiplier   1384/01/21     CAD topics 6,7   Altera EPLDs, Altera FPGAs   1384/01/23     CAD topics 7,8   Altera FPGAs, Xilinx FPGAs   1384/01/28     CAD - topics 8,9   Xilinx FPGAs, Actel FPGAs   1384/01/30     Verilog - topics 5,6   Function & Task - Parameters   1384/02/04     Verilog - topic 6 & Example   Parameter,... - Cash Register   1384/02/11     Verilog - topic 7   UDP   1384/02/13     Verilog - topic 7 & CAD - topic 10   Pin-to-Pin Delay, Design Flow for FPD   1384/02/18     Example   Simple CPU Design   1384/02/20     Solve sample midterm exam      1384/02/22     Midterm Exam      1384/02/25     Solve midterm exam      1384/02/27     Verilog - topic 8   Switch-Level & Strength   1384/03/01     Verilog - topic 9 & CAD - topic 11   File Handling & Field Programmable SOCs   1384/03/03     Solve sample final exam

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Updated Tuesday 2005-05-24 17:00