Digital System Design 40-223 
  CE Department- Sharif University of Technology 1st semester, 1384-85 - Group 1 

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Announcments

  1384-11-09 January 29, 2006 03:44 PM  
Final exam grades (CAD section) announced. See the Grades section

-- Gharehbaghi

  1384-11-08 January 28, 2006 11:00 AM  
Assignments marks are announced. Find them under the "Grades" tab.

--Goudarzi

  1384-11-01 January 21, 2006 11:34 AM  
Final exam grades for the Verilog HDL part of the course are announced. Find them under the "Grades" tab.

--Goudarzi

  1384-09-27 December 18, 2005 04:13 PM  
MidTerm grades of the CAD-FPGA part of the course are announced. Full score is 100.

-- Gharehbaghi

  1384-09-27 December 18, 2005 10:07 AM  
MidTerm grades of the Verilog part of the course are announced. Full score is 50.

--Goudarzi

  1384-09-08 November 29, 2005 10:24 AM  
Mid-term examination:
 Date: Saturday Azar 12th.
 Time: 16:30-18:30
 Place: Bargh-1

-- Gharehbaghi

  1384-08-22 November 13, 2005 10:30 AM  
Assignment 4 is announced. Deadline: Aban 29th.

--Goudarzi

  1384-08-15 November 06, 2005 12:23 PM  
Mid-term examination:
Exam is scheduled for Saturday Azar 12th. The exact time and place shall be announced soon.

--Goudarzi

  1384-08-15 November 06, 2005 12:22 PM  
Assignment 3 is announced. Deadline: Aban 22nd.

--Goudarzi

  1384-08-08 October 30, 2005 12:40 PM  
Assignment 2 is announced. Deadline: Aban 15th.

--Goudarzi

  1384-08-01 October 23, 2005 02:20 PM  
1. Assignment 1 is announced. Deadline: Aban 8th.
2. Some useful resources are put under the "Resources" link.

--Goudarzi

Instructor:
Maziar Goudarzi, Amir Massoud GharehBaghi
(goudarzi [AT] sharif [DOT] edu, amgh [AT] mehr [DOT] sharif [DOT] edu)

3 Units
Sunday, Tuesday: 10:30-12:00
Room: 205

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