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Looking for an opportunity to realize the digital equipment you've always been dreaming of? Take the chance. Attend our first FPGA Design Contest for free and win the prize while realizing your dream. Aimed at :  · Encouraging CE-HW and EE students toward digital design using FPGAs  · Promote effective use of HDLs in everyday digital design tasks  · Enriching our Programmable Logic Design Laboratory in terms of supplemental facilities and experiment platforms we warmly welcome you and your student team to attend the event	Important Dates Registration deadline: Thursday Jan. 17th (Day 27th) Paper submission deadline: Thursday Feb. 21st (Esfand 2nd) Final presentation session: Wednesday Mar. 13th (Esfand 22nd)

FPGA Desgin Contest

Computer Engineering Dept., Sharif Univ. of Tech