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6216, |
E-mail: hkooti@uci.edu |
Hessam
Kooti
Research Interests:
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Embedded Systems
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Low Power Design
§
Reconfigurable Computing
§
VLSI
§
CAD Tools
Education:
PhD in Computer Engineering, Sep. 2008 – Present
Computer Science Department,
Supervisor: Doctor
Eli Bozorgzadeh
M.Sc. in Computer Hardware Engineering, Sep. 2006
– July 2008
Computer Engineering Department,
Sharif
·
First Year GPA (out of 20): 18.64
Thesis Title: “Evaluation of
Power Consumption in Deadlock Recovery Routing Algorithms and
improving Power-Delay Product (PDP)”
Supervisor: Doctor
Shaahin Hessabi
B.Sc. in Computer
Hardware Engineering, Sep. 2001 – Feb. 2006
Computer Engineering Department, Sharif
·
Overall GPA (out of 20): 15.64
·
Last Two Years GPA: 16.30
Thesis Title: “Floating-Point
Adder with Stored Unibit Transfer (SUT): A Study of
Delay and Area”
Supervisor: Doctor Ghasem Jaberipour
Honors and
Awards:
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Ranked
1st among
more than 300,000 participants in the national university entrance exam for
M.Sc. degree
§
Ranked 1st among M.Sc. students of Computer
Architecture major (Sharif Univ. of Tech.)
§
Ranked 187th among
more than 1,000,000 participants in the national university entrance exam (Konkoor)
Experiences:
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Research Assistant in NoC and Reconfigurable Computing Lab 2006-2008
I am working under
supervision of Prof. Shaahin Hessabi.
My current work includes researching deadlock recovery routing
techniques in NoC and implementing them in
VHDL and studying and improving Power Delay Product.
§
Fannavari Moje
Novin Co. 2005-2006
I worked with
several protocols to communicate with various hardwares.
I worked with GPIB protocol to read data from a
Spectrum. I also work with serial communication to program a
Synthesizer and read data from a GPS card.
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Teaching Assistant
I have been TA for “Microprocessors”,
“Hardware Description Languages”, “Probability and Statistics”, “Theory of
Machines
and
Languages” and I am Instructor of Digital Design Lab in current semester.
Accomplished Academic Projects:
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Floating-Point Adder with
Stored Unibit Transfer (SUT): A Study of Delay and Area
(B.Sc. thesis) – Professor Ghasem
Jaberipour
In this project operands were in SUT
representation and the proposed adder had no carry propagation. I implemented
this
adder in
VHDL and analyzed its delay with simulation. Numbers of gates of this adder were
also counted to have an estimation
for
its area.
§
Stochastic Multicast
Wormhole Routing on NoC
I implemented stochastic routing on NoC
proposed by P. Bogdan et al "Stochastic
Communication: A New Paradigm for Fault-Tolerant
Networks-on-Chip", VLSI Design 2007. I improved the algorithm by employing wormhole switching
and adding adaptively to
the
routing technique and changing the probability of each link to reduce power
consumption and increase performance.
§
Implementation of a Theft
Detector with Ultra-Sonic Sensors (Implemented on board)
·
Implemented by 8051
Microcontroller
·
Detects any movement
and alarm
·
Password-protected
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A Compiler for Predefined
Syntax in JAVA
I implemented a compiler's front end for a defined grammar.
The language incorporates mathematical/logical operations,
loops, conditional branches and arrays. It also features
function calls including recursive function calls. I also implemented a
behavioral simulator of the processor to execute the assembly code
generated by the compiler.
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Full Function ALU with
Floating Point in VHDL
·
Including
Floating-Point Operations
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Implementation of a
Dot-Matrix LED Board (Implemented on board)
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Rat-in-Maze in Verilog
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Simulator of Cache
Controller in Verilog
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HTTP Server in JAVA
Technical
Skills:
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Programming Languages:
Java, C#, C++, Assembly
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Hardware Languages: VHDL, Verilog
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Operating Systems: Windows, Linux
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CAD Tools: Modelsim, ORCAD, PSPICE, MaxPlus, Leonardo, MATLAB