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10
Apt., No. 31, Mahraam Str., YossefAbad,
Tehran , Iran |
Home
Phone: +98-21-88603018 Cell Phone: +98-9126970481 E-mail: kooti@ce.sharif.edu |
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Hessam Kooti
Acquiring
research position as PhD student in the field of Computer Engineering
§ Embedded Systems
§ Low Power Design
§ Reconfigurable Computing
§ VLSI
§ CAD Tools
M.Sc. in Computer Hardware
Engineering, Sep. 2006 – Present
Computer
Engineering Department, Sharif University of Technology, Tehran, Iran
·
First
Year GPA (out of 20): 18.50
Thesis Title: “Evaluation of Power Consumption
in Deadlock Recovery Routing Algorithms and
improving
Power-Delay Product (PDP)”
Supervisor: Professor Shaahin Hessabi
B.Sc. in Computer
Hardware Engineering, Sep. 2001 – Feb. 2006
Computer
Engineering Department, Sharif University of Technology, Tehran, Iran
·
Overall
GPA (out of 20): 15.64
·
Last Two
Years GPA: 16.30
Thesis Title: “Floating-Point Adder with Stored Unibit Transfer
(SUT): A Study of Delay and Area”
Supervisor: Professor Ghasem Jaberipour
§ Ranked 1st among more than 300,000 participants in
the national university entrance exam for M.Sc. degree
§ Ranked 1st among M.Sc. students of Computer
Architecture major (Sharif Univ. of Tech.)
§ Ranked
187th among more than 1,000,000 participants in the national university
entrance exam (Konkoor)
§ Research Assistant in NoC and Reconfigurable
Computing Lab 2006-2008
I am working under supervision of Prof. Shaahin Hessabi. My
current work includes researching deadlock recovery routing
techniques in NoC and implementing them in VHDL and studying and
improving Power Delay Product.
§ Fannavari Moje Novin Co. 2005-2006
I worked with several protocols to communicate with various
hardwares. I worked with GPIB protocol to read data from a
Spectrum. I also work with serial communication to program a
Synthesizer and read data from a GPS card.
§ Teaching Assistant
I have been TA for “Microprocessors”, “Hardware
Description Languages”, “Probability and Statistics”, “Theory of Machines
and Languages” and I am Instructor of Digital Design Lab
in current semester.
§ Floating-Point Adder with Stored Unibit Transfer
(SUT): A Study of Delay and Area
(B.Sc. thesis) – Professor
Ghasem Jaberipour
In this project operands were in SUT representation and
the proposed adder had no carry propagation. I implemented this
adder in VHDL and analyzed its delay with simulation.
Numbers of gates of this adder were also counted to have an estimation
for its area.
§ Stochastic Multicast Wormhole Routing on NoC
I
implemented stochastic routing on NoC proposed by P. Bogdan et al
"Stochastic Communication: A New Paradigm for Fault-Tolerant
Networks-on-Chip",
VLSI Design 2007. I improved the algorithm by employing wormhole switching and
adding adaptively to
the
routing technique and changing the probability of each link to reduce power
consumption and increase performance.
§ Implementation of a Theft Detector with Ultra-Sonic
Sensors (Implemented on board)
·
Implemented by 8051 Microcontroller
·
Detects any movement and alarm
·
Password-protected
§ A Compiler for Predefined Syntax in JAVA
I
implemented a compiler's front end for a defined grammar. The language
incorporates mathematical/logical operations,
loops,
conditional branches and arrays. It also features function calls including
recursive function calls. I also implemented a
behavioral
simulator of the processor to execute the assembly code generated by the
compiler.
§ Full Function ALU with Floating Point in VHDL
·
Including Floating-Point Operations
§ Implementation of a Dot-Matrix LED Board
(Implemented on board)
§ Rat-in-Maze in Verilog
§ Simulator of Cache Controller in Verilog
§ HTTP Server in JAVA
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§ Embedded
System Design |
18 (out of 20) |
|
§ Low Power
Design |
18.5 |
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§ Advanced
VLSI |
19.3 |
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§ Hardware
Description Languages |
17.5 |
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§ Advanced
Computer Architecture |
20 |
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§ Compiler |
20 |
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§ Testability |
19.5 |
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§ Advanced
Fault-Tolerant System Design |
17.2 |
§ Programming Languages:
Java, C#, C++, Assembly
§ Hardware Languages:
VHDL, Verilog
§ Operating Systems:
Windows, Linux
§
CAD Tools:
Modelsim, ORCAD, PSPICE, MaxPlus, Leonardo, MATLAB