Niloofar 1 A Synthesizable RISC Processor With Super-Scalar and Out-of-Order Implementation
Introduction
Instruction-Set Architecture (ISA)
Out-Of-Order Implementation
Pipeline Phases
Pipeline Timing
A Simple Simulation
A Simple Data Dependency Case
Memory Instructions
Defying Data Dependency
Structural Hazards
Branch Hazards
Memory Hazards
Synthesis
References
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