Figure2. The simulation of Nf_alu1.v in ModelSim
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The whole IP core of Niloofar 1 have been successfully mapped to an ASIC technology using LeonardoSpectrum. It was CUB provided by AMS [AMS01]. The core have been tested in LeonardoSpectrum for being a fully synthesizable code, so it may be mapped to any other desired standard technology.
The circuit level simulation of the core was needed a lot of time. We had to try this kind of simulation just on a part of the whole processor. One of the ALUs was selected for this issue. A new core was written including the ALU and some of the complementary parts that were needed for the simulation. Refer for the released package contents to find more about the file that contains the implemented core (Nf_alu1.v).
The following program was written for testing the circuit level simulation and its compiled version was included in the Nf_alu1.v.
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alu_t1.s |
| # Testing
the Niloofar 1's implemented ALU movi r1, 0x1234 movi r2, 0x5678 movi r3, 0x9abc movi r4, 0xdef0 movi r5, 0xafcd movi r6, 0xaaaa movi r7, 0xffff nop nop nop nop |
Figure 2 shows the result for the simulation of Nf_alu1.v in ModelSim. In this core the input ports are clk and rst. Program counter and ALU bus were considered as output ports.
Figure2. The simulation of
Nf_alu1.v in ModelSim
It was successfully mapped to 0.6 µm CMOS Si-Gate process technology provided by Austria Micro Systems. LeonradoSpectrum have been used for optimization and technology mapping. RTL schematic have been illustrated in Figure 3. Here is the output of LeonardoSpectrum.
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The Report of LeonardoSpectrum |
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Figure 3. RTL schematic of
Nf_alu1.v in LeonardoSpectrum
An EDIF format netlist file is created by LeonardoSpectrum. It is used as an input netlist file for Tanner EDA L-Edit. In this way the whole circuit level layout of ALU have been created automatically (Figure 4).
Figure 4. Circuit level layout of
Nf_alu1.v in Tanner EDA L-Edit
We have created a .sp format netlist file for ALU using L-Edit. It is used for circuit level simulation by Star H-SPICE. We analyzed the circuit using various frequencies as input clock. The simulation results for 5MHz and 100 MHz may be seen in Figure 5 and Figure 6. Every 4 bits of 16-bit ALU bus is shown by a separate wave, so one may easily compare the output of circuit level simulation with the output of ModelSim.
Figure 5. Circuit level simulation of
Nf_alu1.v in Star H-SPICE, clk = 5 MHz
Figure 6. Circuit level simulation of
Nf_alu1.v in Star H-SPICE, clk = 100 MHz
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