Mehdi Modarressi@Sharif UofT

Mehdi Modarressi

modarressi(AT)ce.sharif.edu

PhD Student

HPCAN (High-Performance Computing Architectures & Networks) Lab.
No. 206, Computer Engineering Department, Sharif University of Technology,

Azadi Ave., Tehran, Iran.

+98 (21) 6616-4636
&

Research Assistant

School of Computer Science, Institute for Studies in Fundamental Sciences(IPM),

Niavaran (Shahid Bahonar) Sq., Tehran, Iran.

+98 (21) 2228-7013 (2172)

I am currently a graduate student at Sharif University of Technology, pursuing a Ph.D. degree in Computer Engineering in the Department of Computer Engineering . My supervisor is Dr. Hamid Sarbazi-Azad and I am a member of the HPCAN (High Performance Computing Architectures and Networks) research group. I am also a research assistant in the IPM (Institute for Studies in Theoretical Physics and Mathematics, Now: Institute for Studies in Fundamental Sciences) school of computer science, Tehran, Iran.

During my M.S. program, I was a member of the ODYSSEY research group at "VLSI Design Lab.” of Sharif University of Technology under supervisory of Dr. Shaahin Hessabi. ODYSSEY is a hardware-software co-design project and stands for "Object-oriented Design and sYntheSiS of Embedded sYstems". To learn more, take a look at the ODYSSEY Web page.

At present, I am working on high-performance and low-power dynamically reconfigurable network-on-chip (NoC) architectures.

Education :

· Ph.D. Student in Computer Engineering
Sharif University of Technology, Tehran, Iran : Since 2007.
Supervisor: Dr. Hamid Sarbazi-Azad.

· M.S. in Computer Engineering
Sharif University of Technology, Tehran, Iran : Sep. 2003 - Jan. 2006 (1382-1384)
Thesis: Design and Implementation of an Object-Aware Cache for Object-Oriented Application Specific Instruction-Set Processors.
Supervisor: Dr. Shaahin Hessabi.

· B.S. in Computer Engineering
Amirkabir University of Technology, Tehran, Iran: Sep. 1999 - Sep. 2003 (1378-1382)
Thesis: Implementing a Modem Compression Protocol (V44) in C and Optimizing the Code for the TMS320C6x Family DSP Processors.
Supervisor: Dr. Mehdi Sedighi

Research Interests :

· High Performance Computer Architectures.

· Network-on-Chips.

· Reconfigurable Computing Systems.

· Parallel Processing and Interconnection Networks.

· HDLs and Programmable Devices.

· Evolvable and Nature-Inspired Digital Systems.

· Computational Biology.

Teaching :

· As an Instructor:

· CE40-483: Hardware Description Languages. (Sharif University of Technology, Current semester (Fall 2008) ) [Course Page Under Construction!]

· CE40-333: Hardware-Software Co-design of Embedded Systems. (Sharif University of Technology, Spring 2008) [Course Page]

· As a Lab. TA:

·         CE40-103: Computer Architecture Lab.(Sharif University of Technology, Summer 2007-Fall 2007)

·         CE40-203: Logic Design Lab. (Sharif University of Technology, Fall 2005)

·         CE40-206: Digital System Design Lab. (Sharif University of Technology, One class per semester since Fall 2004! )

·         CE40-506: Microprocessor Lab. (Sharif University of Technology, Fall 2004-Spring 2005)

Publications :

1. M. Modarressi, H Sarbazi-Azad, M. Arjomand, "A Hybrid Packet-Switched and Circuit-Switched On-Chip Network Based on Spatial-Division Multiplexing", in Design, Automation, and Test in Europe Conference (DATE'09), France, 2009.

2. R. Sabbaghi, M. Modarressi, H. Sarbazi-Azad, " The 2D DBM: An Attractive Alternative to the Simple 2D Mesh Topology for On-Chip Networks”, in The 26th. International Conference on Computer Design (ICCD 2008), USA, 2008.

3. M. Modarressi, H Sarbazi-Azad, A. Tavakkol, "Virtual Point-to-Point Links in Packet-Switched NoCs", in IEEE Computer Society Symposium on VLSI (ISVLSI'08), France, 2008.

4. R. Sabbaghi, M. Modarressi, H Sarbazi-Azad, "A Novel High-Performance and Low-Power Mesh-Based NoC", in The 7th. IPDPS Workshop on Performance Modeling, Evaluation, and Optimization of Ubiquitous Computing and Networked Systems (PMEO), USA, 2008.

5. M. Modarressi, H Sarbazi-Azad, "Power-Aware Mapping for Reconfigurable NoC Architectures", in The 25th. International Conference on Computer Design (ICCD 2007), USA, 2007.

6. S. Hessabi, M. Modarressi, M. Goudarzi, H. Javan-Hemmat, "A Table-Based Application-Specific Prefetch Engine for Object-Oriented Embedded Systems", in International Conference on Embedded Computing Systems: Architectures, MOdeling, and Simulation (IC-SAMOS VI), Greece, Jul. 2006.

7. M. Modarressi, S. Hessabi, M. Goudarzi, "A Reconfigurable Cache Architecture for Object-Oriented Application-Specific Processors", in Canadian Conference on Electrical and Computer Engineering (CCECE'06) , Canada, May 2006.

8. M. Modarressi, H. Javan-Hemmat, S.G. Miremadi, S. Hessabi, M. Najafvand, M. Goudarzi, M. Mohamadzade, "A Fault-Tolerant Approach to Embedded-System Design Using Software Standby Sparing", in The 11th. International CSI Computer Conference(CSICC'06), Iran, Feb. 2006, pp.77-84.

9. M. Modarressi, S. Hessabi, M. Goudarzi, "A Data Prefetching Mechanism for Object-Oriented Embedded Systems Using Run-Time Profiling", in The Third IEEE Symposium on Electronic Design, Test, and Applications (DELTA'06), Malaysia, Jan. 2006, pp.249-254.

10. M Modarresi, H Sarbazi-Azad, "Parallel 3-Dimensional DCT Computation on k-Ary n-Cubes ", in The 8th International Conference on High Performance Computing in Asia Pacific Region (HPC-Asia 2005), China, Nov. 2005, pp.91-97.

11. M. Modarressi, M. Goudarzi, S. Hessabi, "Application-Specific Hardware-Driven Prefetching To Improve Data Cache Performance", in The Tenth Asia-Pacific Computer Systems Architecture Conference (ACSAC'05), Springer-Verlag LNCS Series, Singapore, Oct. 2005, pp. 761-774.