Implementing and Evaluating an Object-Aware Cache

Project Code: OA-Cache CS

Project Level: BS thesis, or MS/PhD course project. With some additions can also be taken as an MS thesis.

Abstract

In an OO-ASIP the processor is aware of the class method that is being executed at any point in time. In this project, we want to take advantage of this additional information to prefetch the (most probably) accessed data so as to make them hit the cache when actually accessed by the running class method code; we call such a cache an “object-aware cache”. The usefulness of object-awareness has been mathematically proven in a previous publication. This project is to implement a cache simulator to quantitatively compare a traditional and an object-aware cache for a set of OO benchmarks. The results are expected to be published in a journal paper covering the mathematical and experimental analysis and figures.

Motivation

• The additional information about the running program in an OO-ASIP
• The significant effect of cache hit-ratio in overall performance of any processor, specifically in embedded systems where the cache size is limited due to size, power, and weight constraints.

Definition

A cache simulator is to be implemented to analyze cache performance of OO applications. The simulator must be able to operate in two modes: a traditional cache, and an object-aware cache. Specific architecture of the OO-ASIP must be considered by the simulator tool to report realistic figures. The simulator is to be run for a set of standard OO benchmarks (to be searched and approved during the project accomplishment). The results must be analyzed and compared to the theoretical figures; any inconsistency must be carefully analyzed and corrections must be applied. The project is considered finished when the paper covering theoretical and experimental results is completed, presented for the ODYSSEY project members, and submitted to an appropriate journal (after probable corrections suggested in the presentation).

This project can also be taken as an MS thesis. In this case, some additional tasks shall be added regarding Object-aware cache implementation and improvements.

Objectives

• Implement a cache simulator for quantitative comparison of traditional and object-aware caches (This can also be published as a conference paper)
• Evaluate cache performance for some OO benchmarks
• Present and analyze the results
• Publish the results in a (journal) paper.

Student Prerequisites

• High programming skills
• “Computer Architecture” course (Good to have also passed “Advanced Computer Architecture” or “Advanced Microprocessors” course)
• If taken as an MS thesis:
  • High experience in hardware design
  • Familiarity with the SystemC language

Interaction with Others

1. In general, can be done all alone.

Abbreviations

OO-ASIP:              Object-Oriented Application-Specific Instruction Processor