Currently Defined Sub

Note: To-be-taken-now projects are hyperlinked to their full definition. Other projects are not to be taken at the moment.

	Title	Code	Available?
PhD Theses	ASIP-Based Design of Embedded Systems from Object-Oriented System-level Models	Design methodology	No
MS Theses	Design and Implementation of an Object-Oriented ASIP Tailored to the JPEG Decompression Algorithm	JPEG OO‑ASIP	Yes
	Programming a JPEG Object-Oriented ASIP to Implement the MPEG2 Decompression Algorithm	MPEG2	Yes
	System-level Power & Area Management in Object-Oriented ASIPs	System-Level Power & Area	Yes
	Mapping Concurrent Object-Oriented Applications onto a Given Multiprocessor OO-ASIP Platform	App-to-Platform Mapping	No
	Design and Implementation of a Simple Network Processor and an Extending Application of it Using the ODYSSEY Methodology	Network Processor	Yes
	Design of a Simple C++-like Object-Oriented Language Tailored to Embedded System Design	Simple OO Language	Yes
MS/PhD Course Projects or BS Theses	A Case Study on Implementing System-level Area-Management in Object‑Oriented ASIPs	Area Management CS	Yes
	A Case Study on Implementing Multiprocessor Platforms of Object-Oriented ASIPs	Multiprocessor CS	Yes
	Optimum Multiprocessor OO-ASIP Design for a Given Object-Oriented Model	Optimum Multiprocessor	No
	Implementing and Evaluating an Object-Aware Cache	OA-Cache CS	Yes
	Implementing and Comparing two Approaches to Access Objects’ Attributes: On-demand Access vs. Burst Access	On-demand or Burst OMU CS	Yes
	Implementing and Evaluating an Evolvable Instruction-Set Processor	Evolvable Processor CS	Yes
	A Case Study on Implementing a Multithreaded OO‑ASIP	Multithreading CS	Yes
	A Case Study on Implementing a VLIW OO‑ASIP	VLIW CS	Yes
	A Case Study on Applying Tomasulo Dynamic Scheduling to the OO-ASIP Microarchitecture	Tomasulo CS	Yes
	A Case Study on Applying Score-Boarding Dynamic Scheduling to the OO‑ASIP Microarchitecture	ScoreBoarding CS	Yes
	A Survey on Issues in Network Processing, Network Processor Architectures, Challenges and State of the Art in Network Processing Field	Network Processing Survey	Yes
BS Theses	Developing an Integrated Development Environment (IDE) for the ODYSSEY Design Methodology	IDE +Debugger	Yes
	Synthesis of an Object-Oriented ASIP from Register-Transfer Level (RTL) down to a target FPGA, CSoC, and/or Demonstration Board	Logic-level Synthesis	No
	Synthesizing OO-ASIP from Java Models and Compiling Java for Execution on an OO-ASIP	Java Synthesizer & Compiler	Yes

Currently Defined Sub-projects

Composition of the Tasks into Tracks