Synthesis of an Object-Oriented ASIP from Register-Transfer Level (RTL) down to a target FPGA, CSoC, and/or Demonstration Board

Project Code: Logic-Level Synthesis

Project Level: BS internship or course project

Definition

Currently, the ODYSSEY project synthesizes an object-oriented ASIP (OO-ASIP) in the SystemC language from the initial class library in C++. This OO-ASIP is in behavioural level and must conform to some rules to be synthesizable by behavioural synthesis tools. You are to make experiments with all available synthesis tools (currently just one) that accept SystemC as input and identify the one that best suits our needs and gives the best results. Then, the synthesizability rules that the tool imposes should be identified and discussed with our synthesis-tool writer(s). The steps (tools and commands) required to synthesize an OO-ASIP down to a target FPGA, CSoC, or demonstration board are to be found and the required scripts must be provided. The project is considered finished when a complete synthesis path is provided (in terms of automatic scripts) that accepts an OO-ASIP in SystemC and provides synthesis results such as area and speed.

The project can be extended to also produce power estimation results; in this case, it can be obtained as a BS thesis.

Objectives

Student Prerequisites

Interaction with Others

  1. In general, can be done all alone.