Hi! I'm Hamed Abbasitabar, a graduated MSc. student of Computer Engineering.

About Me

I received my BSc. degree from Amirkabir University of Technology (Poly Technique) Tehran, Iran in 2011 with final thesis titled "Evaluation of Soft Errors Effects on LEON-based Embedded Systems" under supervision Dr. Zarandi. I completed MSc. degree in Sharif University of Technology in 2013. My MSc thesis was "A Reconfigurable and Adaptive Shared-Memory Architecture for GPUs" which is done in HPCAN laboratory under supervision of Dr. Sarbazi-Azad.

Publications

  • Mohammad Hossein Samavatian, Hamed Abbasitabar, Mohammad Arjomand and Hamid Sarbazi-Azad, “An Efficient STT-RAM Last Level Cache Architecture For GPUs,” Design Automation Conference (DAC) 2014, San Francisco, CA, USA. (Download)(Link)
  • Hamed Abbasitabar, Hamid R. Zarandi and Ronak Salamat, “Susceptibility Analysis of LEON3 Embedded Processor against Multiple Event Transients and Upsets,” International Conference on Computational Science and Engineering (CSE) 2012, Paphos, Greece.(Download)(Link)

Projects

A simulation approach for resource-sharing on GPUs with the multi-programming feature.

We are currently working on an approach for sharing unused portion of resources on SMs while running multiple programming on GPUs simultaneously. Our goal is to implement an simulation method based on execution on workloads on GPGPU-Sim and post processing the collected data to gather required information. To satisfying this purpose, we changed GPGPU-Sim for adding extra features and obtaining only the required informations to increase simulation speed. We generates numerous configuration files, meeting the hardware requirements, and runs the programs with variety of configurations. To complete our simulation steps, we develop a JAVA program for reading the results of individual program execution, classifying the raw data and calculating all needed performance metrics. (Further information will be added).

A fault-injection platform for evaluating single and multiple transient and upsets for VHDL and Verilog described circuits.

A complete description and use instruction will be added very soon.

Contact

Don't hesitate to get in touch with me if necessary.

Address:

Department of Computer Engineering, Sharif University of Technology, Azadi Ave., Tehran, Iran


Email:

[my_last_name]@ce.sharif.edu