Welcome!

I am Mohammad Reza Jokar, an M.Sc. graduate from the Computer Engineering Department of Sharif University of Technology. My research interests include computer architecture, memory systems and CPU-GPU architectures.
I did my M.Sc. under the supervision of Professor Hamid Sarbazi-Azad, in the HPCAN group at the Computer Engineering Department of Sharif University of Technology. During M.Sc. period, I worked on the use of nonvolatile memories in the memory hierarchy.

Education

  • 2012-2014 : M.Sc. in Computer Engineering
    Sharif University of Technology, Tehran, Iran. (GPA= 18.83 / 20)
  • 2008-2012 : B.Sc. in Computer Engineering
    Shahid Bahonar University of Kerman, Kerman, Iran. (GPA= 17.07 / 20)
  • Publications

  • M. R. Jokar, M. Arjomand, and H. Sarbazi-Azad, "Sequoia: A High-endurance NVM-based Cache Architecture," accepted for publication in IEEE Transactions on VLSI Systems (TVLSI).
  • (IEEE Link)

  • Abstract : Emerging nonvolatile memory technologies, such as spin-transfer torque RAM or resistive RAM, can increase the capacity of the last-level cache (LLC) in a latency and power-efficient manner. These technologies endure 10^9-10^12 writes per cell, making a nonvolatile cache (NV-cache) with a lifetime of dozens of years under ideal working conditions. However, nonuniformity in writes to different cache lines considerably reduces the NV-cache lifetime to a few months. Writes to cache lines can be made uniformly by wear-leveling. A suitable wear-leveling for NV-cache should not incur high storage and performance overheads. We propose a novel, simple, and effective wear-leveling technique with negligible performance overhead of <0.4% for memory-intensive workloads. Our proposal consists of two mechanisms: 1) a wear-leveling mechanism within each cache set that slightly increases main memory write-back traffic and LLC miss rate and 2) a novel technique to reduce cache interset variation which causes minimum interference with normal cache operation. Using these mechanisms, we show that the lifetime of the NV-cache is boosted up to 13x for different cache configurations.
  • Skills

  • Programming Languages : C/C++, C#, Python, MATLAB
  • Simulation Tools : Gem5, Virtutech Simics, GPGPU-Sim, Gem5-GPU, CACTI
  • HDL : Verilog, VHDL
  • Operating Systems : Windows, Linux
  • Typesetting : Microsoft Office, LATEX
  • Contact

  • Office : HPCAN Lab (Room 701), Department of Computer Engineering, Sharif University of Technology, Azadi Avenue, P.O. Box 11155-9517, Tehran, Iran.
  • Email : mylastname@ce.sharif.edu
  • Phone : (+98) 917 119 1443